Recently, in the field of display device, a current-driven optical device has been developed, the light intensity of which varies with a value of the current flowing there through. For example, there is a display device in which an Organic Light Emitting Device (OLED) is adopted as a light emitting device for a pixel. Different from a liquid crystal device, the OLED is a self-luminescence device. In a display device in which the OLED is adopted, classification of a color is obtained by controlling the current in the OLED.
As with a liquid crystal display, a driving system in the OLED may be a passive matrix system or an active matrix system. The passive matrix system has a simple structure; however, it is difficult to achieve a display device with large size and high resolution by adopting the passive matrix system. Therefore, the development of the active matrix system is popular. In the active matrix system, a transistor is driven to control the current in the light emitting device provided for each pixel.
Presently, in designing an Active Matrix Organic Light Emitting Diode (AMOLED), especially a large-size substrate, unevenness of the current in the OLED is caused due to the unevenness and instability of a Thin Film Transistor (TFT) during its manufacturing process. To offset the threshold voltage shift (Vth Shift) due to the unevenness of the TFT during the manufacturing process of a backplane, and the instability of the TFT due to turning on a bias voltage for a long time, it is necessary to design a compensation circuit. In the conventional art, a P-type Metal Oxide Semiconductor (Pure PMOS) driving circuit is used, and the driving circuit outputs an effective low level; but during node initialization, threshold detection and data inputting, the OLED device needs to be turned off. Due to the single PMOS, the Pure PMOS is turned on in the case of a low voltage of the gate electrode, and turned off in the case of a high voltage of the gate electrode. The Pure PMOS driving circuit generally outputs effective low level. Therefore the signal output from the Pure PMOS driving circuit needs to be inverted, so that the OLED device is turned off. The inverting of the signal is achieved by a light emitting-controlled (EMIT) driving circuit in the conventional art.
To achieve the inversion into a high level from a low level, an inverter is proposed in the conventional art, the structural diagram of which is shown in FIG. 1a. The inverter includes an N-type TFT and a P-type TFT. A gate electrode of the P-type TFT is connected to a gate electrode of the N-type TFT, and is connected to an input terminal IN together with the gate electrode of the N-type TFT. A source electrode of the P-type TFT is connected to a high-voltage signal (VGH). A drain electrode of the N-type TFT is connected to a low-voltage signal (VGL). A drain electrode of the P-type TFT Is connected to a source electrode of the N-type TFT, and is connected to an output terminal (OUT) together with the source electrode of the N-type TFT. FIG. 1b is a control timing diagram of the CMOS inverting circuit in FIG. 1a. It can be seen from FIG. 1b that when the IN is in high level, the P-type TFT is turned off, the N-type TFT is turned on, and the OUT outputs a low level signal; and when the IN is in a low level, the P-type TFT is turned on, the N-type TFT is turned off, and the OUT outputs a high-level signal. Since such PMOS inverter has both the P-type TFT and the N-type TFT, the manufacturing process is complicated, and the cost is high as compared with the pure P-type inverter or the pure N-type inverter.
To achieve the inversion into a high level from a low level, another inverter is proposed in the conventional art, the structural diagram of which is shown in FIG. 2a. The inverter includes two P-type TFTs, i.e., a first TFT and a second TFT. A gate electrode of the first TFT is connected to an input terminal IN, a source electrode of the first TFT is connected to a high-voltage signal (VGH), and a drain electrode of the first TFT is connected to an output terminal (OUT). A gate electrode and a drain electrode of the second TFT each are connected to a low-voltage signal (VGL), and a source electrode of the second TFT is connected to the OUT. FIG. 2b is a control timing diagram of the pure PMOS inverting circuit in FIG. 2a. It can be seen from FIG. 2b that when the IN inputs high level, the first TFT is turned off, the OUT outputs low level due to the Diode connection manner of the second TFT (in which the gate electrode and the drain electrode of the second TFT each are connected to the low-voltage signal VGL), and the voltage of the low level is higher than the VGL by Vth. When the IN is in low level, the first TFT and the second TFT each are turned on, the OUT outputs high level. However, in the above circuit, the OUT is connected to both the VGH and the VGL, and if the TFT is turned on/off completely, the OUT is connected to either VGH or VGL, and the OUT takes the VGH as the high voltage and the VGL as the low voltage. The above circuit has the problem that the two TFTs are turned on at the same time, and with this, the OUT outputs the intermediate level between the VGH and the VGL due to the voltage-division function. That is to say, the high/low output level is between the VGH and the VGL, which is not enough, then the power supply continuously supplies power, the power consumption is increased. Further, since the output level is not enough (input ranges from −5V to 10V, and output ranges from −4.43V to 5.07V), the TFT in the pixel cannot be controlled effectively, so that the compensation circuit cannot work effectively.